PURPOSE: To provide a frequency divider capable of dividing the frequency of a clock input with high frequency.
CONSTITUTION: This frequency divider is constituted of a shift register 1 including plural flip flops(FFs) previously initialized at the same level by a reset signal RESET and having an input signal as a clock and a circuit means 3 for inverting an output from the register 1, feeding back the inverted signal to the input of the register 1, and when a frequency dividing number is an odd number, by-passing one stage of the register 1 in accordance with the output level of the register 1. A circuit means for by-passing one stage of the register 1 in accordance with the output level of the register 1 when the frequency dividing number is an even number is omitted.
KOJIMA KOJI
AKAZAWA TAKASHI
HATANO YUJI
