PURPOSE: To generate a clock whose duty factor is 50% by applying 1/odd number frequency division to an inputted clock whose duty factor is 50%.

CONSTITUTION: An external input signal to a signal line 105 is subject to 1/3 frequency division by JK flip-flop circuits 101,102. Furthermore, a signal from a positive logic output terminal 106 of the JK flip-flop 101 is delayed by a D flip-flop 103 and signals at a positive logic output terminal 108 of the JK flip-flop 102 and at a positive logic output terminal of the D flip-flop 103 are ORed by an OR logic element 104. Then an output signal whose duty factor is 50% is outputted to a signal line 110.