Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
FREQUENCY DIVIDER AND PLL CIRCUIT
Document Type and Number:
Japanese Patent JP2004364105
Kind Code:
A
Abstract:

To improve the maximum operation frequency of a prescaler circuit 1 without depending on the process of an element.

Flip-flops FF1 to FF3 apply 1/4-frequency division to a clock inputted to a clock terminal by feedbacking the output of the flip-flop FF3 of a last stage to the flip-flop FF1 of a first stage. Also, the flip-flops FF1 to FF3 apply 1/5-frequency division to a clock inputted to the clock terminal by feedbacking the output of the flip-flop FF2 to the flip-flop of the first stage. An OR circuit Z1 and an AND circuit Z2 feedback the output of the flip-flop FF3 of the last stage to the flip-flop of the first stage in accordance with a control signal S and outputs of flip-flops FF3 to FF5. A delay circuit Z3 delays an input clock INCLK inputted to the flip-flops FF1 and FF2.


Inventors:
MINAMI KOICHIRO
Application Number:
JP2003162111A
Publication Date:
December 24, 2004
Filing Date:
June 06, 2003
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SONY CORP
International Classes:
H03K23/66; H03L7/08; (IPC1-7): H03K23/66; H03L7/08
Attorney, Agent or Firm:
Takeshi Hattori