To provide a frequency divider capable of attaining high frequency operations with low power consumption.

A latch circuit acting like a unit element of the frequency divider is configured with an ECL logic circuit provided with inductors L1, L2 as loads, as shown in Fig.1, an output of the latch circuit is selected to be a value at which the impedance matching of the circuit output at the operating frequency is optimized in combination with the inductors L1, L2, and the latch circuit is connected to a next stage circuit via capacitors C1, C2 to configure the frequency divider. Since the inter-stage impedance of each latch circuit configuring the frequency divider can be matched, the performance of transistors can maximally be developed and high speed frequency division operations can be attained with a consumed current less than that of ECL logic frequency dividers of prior arts.