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Title:
FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JP2010193373
Kind Code:
A
Abstract:

To provide a frequency divider capable of increasing an operation frequency in a simple circuit configuration.

In the case where an operation control signal ENB is shifted to 'H' level and a clock signal VCO and a frequency dividing signal VCO_div2 are stopped at 'L' level and 'H' level, in a frequency divider, a control signal A output from a three-input NAND gate 14 is turned to 'L' level and a trigger signal VCO_delay output from an exclusive NOR gate 10 becomes 'H' level. The trigger signal VCO_delay is being input to a trigger terminal T of a flip-flop 11_1, the frequency dividing signal VCO_div2 being output from the flip-flop 11_1 is shifted from 'H' level to 'L' level, and the flip-flop 11_1 is brought into a reset state.

COPYRIGHT: (C)2010,JPO&INPIT


Inventors:
TARUMI AKIHIRO
Application Number:
JP2009038028A
Publication Date:
September 02, 2010
Filing Date:
February 20, 2009
Export Citation:
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Assignee:
KAWASAKI MICROELECTRONICS INC
International Classes:
H03K23/00; H03K21/00; H03L7/08
Domestic Patent References:
JPH0983353A1997-03-28
JPH0661843A1994-03-04
Attorney, Agent or Firm:
小杉 佳男
山田 正紀