To provide a frequency divider capable of reducing current consumption while ensuring a performance as a frequency divider.

Frequency divider circuits 10, 30, 50 are connected in series and in order to reduce current consumption of an entire frequency divider, the frequency divider circuits 10, 30, 50 are divided into a low-potential side first group G1 and a high-potential side second group G2. A low-potential side power supply terminal 17 of the frequency divider circuit 10 that belongs to the first group G1 is connected to a low-potential power source VSS. Furthermore, high-potential side power supply terminals 36, 56 of the frequency divider circuits 30, 50 that belong to the second group G2 are connected to a high-potential power source VDD. Moreover, a high-potential side power supply terminal 16 of the frequency divider circuit 10 is connected to low-potential side power supply terminals 37, 57 of the frequency divider circuits 30, 50.