Title:
FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JP3707203
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a frequency divider where a clock signal is frequency- divided at frequency division ratios including a half cycle of the clock signal.
SOLUTION: The frequency divider is made up of a 1/(2n+1) frequency divider 1, a duty adjustment device 2, a (n+1/2) clock delay circuit 3 and a changeover device 4, a received clock CKo is frequency-divided at the 1/(2n+1) frequency divider 1 by 1/(2n+1) and then a duty factor of the signal frequency- divided by the duty adjustment device 2 to be 1:2n. The signal whose duty factor is adjusted is delayed at the (n+1/2) clock delay circuit 3 by (n+1/2) clocks and the delayed signal is given to the changeover device 4. On the other hand, even a signal before the delay outputted from the duty adjustment device 2 is given to the changeover device 4 and either of the two signals is selected by the clock CKo, and a frequency division output of CKo/(n+1/2) is obtained from the changeover device 4.
Inventors:
Tatsuya Kubo
Application Number:
JP13240397A
Publication Date:
October 19, 2005
Filing Date:
May 22, 1997
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H03K23/00; H03K23/64; (IPC1-7): H03K23/00; H03K23/64
Domestic Patent References:
| JP7288467A | ||||
| JP9261048A | ||||
| JP4104614A |
Attorney, Agent or Firm:
Takeshi Hattori
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