To provide a frequency division circuit of which the operation speed can be increased.

A master circuit 10 comprises a differential amplification circuit 10a for taking in an output of the frequency division circuit in response to a clock CK+ and a latch circuit 10b for holding an output of the differential amplification circuit during a clock period. A slave circuit 20 comprises a differential amplification circuit 20a for taking in an output of the master circuit in response to a clock CK- and a latch circuit 20b for holding an output of the differential amplification circuit 20a during a complementary clock period and outputs a signal resulting from dividing the frequency of the clock. Constant current sources 2 and 3 for latch circuits are provided separately from a constant current source 1 for differential amplification circuits. Differential pairs of transistors in the differential amplification circuits are connected to the constant current source in response to each clock. Differential pairs of transistors in the latch circuits are directly connected to independent constant current sources.

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