PURPOSE: To obtain the output of 50% duty factor for 1/(2n-1)-fold frequency of an original signal by decoding the output of a 2n-1 counter and holding one signal of the output in a register circuit with a clock and holding the other there in the inverted clock and synthesizing outputs by OR to obtain an input signal of a frequency divider.

CONSTITUTION: The output signal of a (2n-1)-notation counter 7 which is operated synchronously with an input signal (clock) which should have the frequency divided is decoded by a decoding circuit 8 to take out a signal for the first clock and a signal for the (2n-1)th clock in a period corresponding to (2n-1)- number of clocks. The former signal and the latter are held in flip flops D-FFs 91 and 92 of a register circuit 9 for the period corresponding to one clock by the clock and the inverted clock respectively, and OR between outputs of D-FFs 91 and 92 is operated by an OR circuit 10 and has the frequency divided by 1/2 in a frequency dividing circuit 11 which is operated with said OR as the input. Since the output signal of the D-FF 92 is placed in the just middle between the continuous output signals of the D-FF 91, the output of the 1/2 frequency dividing circuit 11 has 1/(2n-1)-fold frequency of the clock of 50% duty factor.