PURPOSE: To operate the circuit accurately with respect to a change in a duty ratio of a basic clock signal by applying a prescribed logic arithmetic processing to both outputs of 1st and 2nd state generating circuit and the basic clock signal as logic input signals in advance to generate a required frequency division output.

CONSTITUTION: A hold control signal generating circuit 1 receives a forward hold signal (a) representing suppression in a change in a frequency division output (i) and a clock signal (b) and generates each of control signals c-f for a forward state generating circuit 2 and a reverse state generating circuit 3. The signal (c) among the control signals c-f is a forward delayed hold signal resulting from the signal in a timing synchronously with the start timing of the basic clock (b) converted from the forward hold signal (a) and becomes an input signal to the forward state generating circuit 2. Thus, even when the duty ratio of the basic clock signal is changed, stable frequency division is attained so long as both edges of the clock is made stable.