PURPOSE: To realize the adjustment of the frequency dividing ratios of plural input clock signals and the duty ratio of an output clock signal through the use of the frequency divider circuit of one set portion.

CONSTITUTION: A counter 1 counts a clock signal CLK from an initial value A to a maximum value an initial value setting part 2 set, and frequency-divides the clock signal CLK. A subtracter part 4 subtracts the present count value C of the counter 1 from a threshold B a threshold setting part 3 set, and outputs a result as a sign signal D. A flip flop circuit 7 outputs a pulse signal E only during a period in which the sign signal D is positive or negative in accordance with the input of the sign signal D and the clock signal CLK. A duty adjusting part 6 extends the pulse signal E by the half period of the clock signal CLK, and turns it into a period adjusted pulse signal F, and a selector 5 selects one of the pulse signal E and the period adjusted pulse signal F, and turns it into the output clock signal.