PURPOSE: To realize the frequency divider able to reduce the test time by providing the mode to output an input clock as it is so as to avoid frequency division.

CONSTITUTION: The frequency divider consists of basic blocks connected in cascade. Each block is formed in such a way that a clock input 3 and an output 4 of a T flip-flop 1 are inputted to a multiplexer 2 and a control signal 5 is used to switch the clock input 3 or the output 4 of the T flip-flop 4 and the output is outputted to an output 6. In the frequency divider in which the basic blocks are connected in cascade, a frequency division ratio is optionally set by setting a control signal input of each stage, and when all the stages are set to the mode not frequency-dividing the input signal at test, the clock is directly fed to the logic circuit clock of the frequency divider and the test is conducted in a short time without frequency division time.