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Patent Searching and Data


Title:
FREQUENCY-DIVIDING CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT EQUIPPED WITH THE FREQUENCY-DIVIDING CIRCUIT
Document Type and Number:
Japanese Patent JP2006157849
Kind Code:
A
Abstract:

To provide a frequency divider or the like which can divide the frequency of a clock signal by a desired frequency division ratio.

A frequency divider is provided with a first circuit 10, activating an enable signal according to the frequency dividing ratio of a number according to a division ratio of an input clock signal, a T-shaped flip-flop 20 for outputting a signal PHASE 0 toggled by an input clock signal, when the enable signal is activated, a third circuit 30 for outputting signals PHASE 1-8 which are input clock signals of the signal PHASE 0 sequentially delayed per half-frequency each, a multiplexer 40 selecting a signal according to the division ratio from among the signals PHASE 1-8 to be outputted, and an EXOR gate circuit 50 for generating the second clock signal, by performing an exclusive logical sum calculation with the signal outputted by the signal PHASE 0 and the multiplexer 40.


Inventors:
KOBAYASHI SHINICHIRO
Application Number:
JP2005016445A
Publication Date:
June 15, 2006
Filing Date:
January 25, 2005
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H03K23/64; G06F1/06; G06F1/08
Attorney, Agent or Firm:
Mutsumi Yanase
Masaaki Utsunomiya
Atsushi Watanabe
Harada victory