To provide a frequency divider or the like which can divide the frequency of a clock signal by a desired frequency division ratio.
A frequency divider is provided with a first circuit 10, activating an enable signal according to the frequency dividing ratio of a number according to a division ratio of an input clock signal, a T-shaped flip-flop 20 for outputting a signal PHASE 0 toggled by an input clock signal, when the enable signal is activated, a third circuit 30 for outputting signals PHASE 1-8 which are input clock signals of the signal PHASE 0 sequentially delayed per half-frequency each, a multiplexer 40 selecting a signal according to the division ratio from among the signals PHASE 1-8 to be outputted, and an EXOR gate circuit 50 for generating the second clock signal, by performing an exclusive logical sum calculation with the signal outputted by the signal PHASE 0 and the multiplexer 40.
Masaaki Utsunomiya
Atsushi Watanabe
Harada victory