To provide a frequency-dividing circuit that can obtain various numbers of frequency division with the same constitution and perform stable frequency division even when an input reference clock is fast.

The frequency-dividing circuit is equipped with: a 1st storage circuit which consists of m stages of delay type flip-flops (m: a positive integer) and generates an enable signal of (m+1) frequency division; and a 2nd storage circuit which consists of n stages of delay type flip-flops (n: a positive integer) in which the enable signal is connected to load-hold terminals and generates a clock of (n+1) frequency division. The circuit outputs a clock of (m+1)×(n+1) frequency division.