PURPOSE: To obtain a frequency dividing circuit having a simple constitution and small scale by providing (n) stages of FFs, FF1∼FFn, and an AND circuit which takes the AND of the inverted output of the 1st-stage FF, FF1, and the clock for processing timing of the FFs, FF1∼FFn.

CONSTITUTION: Clocks CLK (1) which are inputted from a control section, etc., (not shown in the figure) at a prescribed speed and have a duty factor of 50% are inputted to an FF 20(1) as clock signals (3) after the AND of the clocks CLK (1) and inverted output Q' of the FF 20(1) is taken by an ANF circuit 30. When the clock signals (3) are inputted, the output of the FF 20(1) is inverted under a condition where a two-input/one-output NOR circuit 50a is 'H' and the output of a NOR circuit 40a becomes 'H'. The FF 20(1) maintains the same state until it is reset. When such operations are repeated at every third period of the clocks CLK (1), the clocks CLK (1) are frequency- divided by three by the positive output Q of the FF 20(1) and, at the same time, output pulses (2) having a duty factor of about 50% are obtained.