PURPOSE: To previously prevent the abnormality of a signal waveform at the time of switching a frequency and to obtain the stable and objective frequency by obtaining a frequency-dividing output from the AND output of an inputted reference signal and the frequency-dividing output.

CONSTITUTION: When a control signal 4 which is inputted to the D input of D type FF1 shows '1', a Q output shows '1' while it is synchronized with a reference clock signal 5. Namely, a reset input 7 shows '1', a D type FF2 is synchronized with the rise of the reference clock signal 5 and the frequency- dividing processing of the signal which is inputted to a clock input CK starts. A frequency-dividing clock 8 obtained by dividing the frequency of the signal 5 twofold is outputted from the output terminal Q to an AND gate 6. The gate 6 executes the AND operation of the reference clock signal 5 and the frequency-dividing clock 8, and a frequency-divided clock signal 3 is outputted. When the control signal shows '0', the frequency-dividing clock signal 8 shows '0', and the frequency-divided clock signal 3 which does not have step-out and which is synchronized with the reference clock signal 5 is outputted from that time.