PURPOSE: To divide the frequency of a clock signal in a duty ratio of 1:1 in the case of odd numbered frequency division.

CONSTITUTION: The frequency dividing circuit is provided with a counter 1 counting a clock signal CLK, a 1st decoder 2 applying a signal '1' to the trigger terminal of a flip-flop 4 when the counted content is (n), and a 2nd decoder to reset the flip-flop 4 and the counter 1 in the falling timing of the clock signal CLK when the counted content is (2n+1). Then a frequency dividing output signal whose duty ratio is 1:1 is outputted form the output signal of the flip-flop 4.