PURPOSE: To obtain a frequency dividing output of (2n+1)/2 from a source oscillating frequency with simple circuit constitution.

CONSTITUTION: This circuit consists of flip-flop circuits FF1-FF4 and an exclusive NOR circuit XNOR, etc. The flip-flop circuits FF1-FF3 are activated synchronously with a clock input signal CLK and the flip-flop circuit FF4 is activated synchronously with an inverted clock input signal CLKB. Since the flip-flop circuit FF4 is activated synchronously with an inverted clock input signal CLKB, the FF4 outputs a signal OUT1 deviated by a half clock from the clock input signal. The output OUT2 of the flip-flop circuit FF3 of shift register constitution and the output OUT1 are processed by the exclusive NOR circuit XNOR, from which a 3/2 frequency dividing signal is obtained.