PURPOSE: To attain the frequency division of a high frequency pulse by inputting a pulse signal having an optional period and an optional duty ratio to the frequency dividing circuit and outputting a pulse signal subjected to 1/N frequency division to the input pulse signal therefrom.

CONSTITUTION: Since the outputs of latches at an even numbered order are all 0 at a time T0, the output 200 of a NAND 20 goes to logic '1', a latch 11 is triggered at the rice T1 of a succeeding input pulse to change the output from logic '0' to logic '1'. This change is delivered to the next-stages of latches 12, 13-1(2N-3), 1(2N-2), and the output of each latch changes from logic '0' to logic '1' at times T2, T3-T2N-3, T2N-2. The outputs of the latches at an even numbered order are all 1 at a time T2N-2, the output 200 of the NAND 20 is changed to logic '0', the latch 11 is triggered at the rice T2N-1 of a succeeding input pulse to change the output from logic '1' to logic '0'. This change is delivered to the next-stages of latches 12, 13-1(2N-3), 1(2N-2), and the output of each latch is changed from logic '1' to logic '0' sequentially.