PURPOSE: To vary the output timing of the frequency dividing circuit to an input clock by providing a first and a second switches for inputting outputs of a first latch circuit and a second latch circuit, respectively, and switching each output of two latch circuits by the switch.

CONSTITUTION: When a CTL signal is L, N type transistors 21, 22 become a turn-off state and N type transistors 23, 24 become a turn-on state, therefore, an output of a signal A1 and an output of a signal B1 are outputted to a Q output and Q output, respectively. Therefore, as for the output signals Q, Q, the output is inverted by synchronizing with a rise of a CL signal. Subsequently, when the CTL signal is H, 21 and 22 become a turn-on state, and 23 and 24 become a turn-off state, therefore, an output of a signal A2 and an output of a signal B2 are outputted to the Q output and the Q output, respectively. Therefore, as for the output signals Q, Q, the output is inverted by synchronizing with a fall of the CL signal. The output of the frequency dividing circuit is frequency-divided into two against the CL signal irrespective of H or L of the CTL signal.