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Title:
FREQUENCY DIVIDING CIRCUIT
Document Type and Number:
Japanese Patent JPH05243976
Kind Code:
A
Abstract:

PURPOSE: To simplify constitution and to easily obtain the output frequency dividing signal of frequency dividing rate excepting for an integer by utilizing one oscillator oscillating a single frequency comparatively low.

CONSTITUTION: The system consists of the oscillator 10 outputting the oscillating signal Ss of the single frequency N. a frequency divider 12 which can switch the frequency dividing rate to K or K+1 and a frequency divider 14 controlling the frequency dividing rate of the frequency divider 12. The frequency divider 12 divides the oscillating signal Ss from the oscillator 10 with the frequency dividing rate K or k+1, outputs it as an output frequency dividing signal So and simultaneously provide it for the frequency divider 14 to L-divide it and to control/change/set the frequency divider 12 to frequency dividing rate K or K+1 with an L-cycle. The frequency dividing rate of the numbers excepting for an integer can be obtained by the closed loop control of 1/{(k+1)-1/L} like this.


Inventors:
YAMAZAKI MASUYO
Application Number:
JP7825292A
Publication Date:
September 21, 1993
Filing Date:
February 28, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K23/64; (IPC1-7): H03K23/64
Attorney, Agent or Firm:
Kihei Watanabe



 
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