PURPOSE: To set a frequency division ratio optionally, by rewriting data in shift registers when performing frequency division by using the shift registers.

CONSTITUTION: Shift registers SR1∼SR3 are driven at the same time by a clock signal CK. The shift registers SR1∼SR3 differ in the number of constituent bits and their input and output terminals are connected mutually. Optional 1-bit outputs of the shift registers SR1∼SR3 are extracted and inputted to a 3-input AND circuit. When the input signals are coincident, the AND circuit generates an output signal. According to data to be written in the shift registers SR1∼SR3, a voltage division ratio is set optionally.