PURPOSE: To realizea frequency dividing clock generating circuit and a screen display device having the circuit with configuration where one-chip conversion is perfectly executed without an exterior capacitor.

CONSTITUTION: Flip-flops 21, 22 and an OR gate 25 are provided and OR of a signal D inverted by the rising of a basic clock A with the signal E inverted by the falling of it is adopted as a frequency dividing clock F. A reset pulse C is outputted at a start end of a synchronizing signal B by the flip-flop 23 and an AND gate 24 and the flip-flops 21 and 22 are reset. Then, the frequency dividing clock F which is synchronized within the permission range in accordance with the synchronizing signal B is generated without exterior capacitors.