PURPOSE: To simplify the configuration of a frequency divider circuit and to enable high frequency division.

CONSTITUTION: An inverter 9 is provided to invert a ripple carry signal 12 of a pulse counter 7 in a programmable counter 17, and the output of the inverter 9 is connected to the enable input of the pulse counter 7. Then, the ripple carry signal 12 is directly connected as a frequency divided value control signal 13 of a dual modulus digital frequency divider 6. The counter operation of the pulse counter 7 is stopped synchronously to the start of the ripple carry signal 12. Further, the count operation of the pulse counter 7 is started again by the output signal of a swallow counter 8, and the ripple carry signal 12 is reset at a low level.