Title:
奇数整数による周波数分割
Document Type and Number:
Japanese Patent JP2008520154
Kind Code:
A
Abstract:
The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CL 1 ) frequency by an odd integer. A digital value is shifted into a set of latches based on the clock signal (CL 1 ) and kept there a predetermined number of half clock cycles. The value is shifted into a following latch delayed with half a clock cycle of the clock signal compared with a previous latch. Then a first (Q 1 ) and a second (Q 6 ) intermediate signal, each provided through information stored in a latch, are interpolated for forming said first output signal (O Q). Because of this it is possible to provide an output signal having edges displaced from clock signal edges, thus allowing a higher resolution than the original clock signal has and in particular, enabling quadrature outputs from a standard odd-integer frequency divider.
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Inventors:
Fundebake, Remco, Say, Ha
Reinalts, Dominicus, M, Way
Reinalts, Dominicus, M, Way
Application Number:
JP2007540795A
Publication Date:
June 12, 2008
Filing Date:
November 09, 2005
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
H03K23/70; H03B19/12; H03K21/00
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito