Title:
FREQUENCY DIVISION CIRCUIT
Document Type and Number:
Japanese Patent JP2015053696
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a frequency division circuit that suppresses a malfunction.SOLUTION: The frequency division circuit includes a shift register for outputting 2×X pulse signals (X is a natural number of two or greater) generated according to a first or second clock signal, and a frequency-divided signal output circuit 102 for outputting a signal generated according to the 2×X pulse signals as a third clock signal having a period X times that of the first clock signal. The frequency-divided signal output circuit includes X first transistors fed at respective gates with different pulse signals of the first to the Xth of the 2×X pulse signals to control whether or not to set a voltage of the signal as the third clock signal at a first voltage, and X second transistors fed at respective gates with different pulse signals of the (X+1)th to the (2×X)th of the 2×X pulse signals to control whether or not to set the voltage of the signal as the third clock signal at a second voltage.
Inventors:
TAKAHASHI KEI
ITO YOSHIAKI
ITO YOSHIAKI
Application Number:
JP2014211540A
Publication Date:
March 19, 2015
Filing Date:
October 16, 2014
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB
International Classes:
H03K23/44; H01L29/786
Domestic Patent References:
| JP2010049791A | 2010-03-04 | |||
| JP2008122939A | 2008-05-29 | |||
| JP2004226429A | 2004-08-12 |