Title:
FREQUENCY DIVISION CIRCUIT
Document Type and Number:
Japanese Patent JP3666078
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a circuit by which plural frequencies can be obtained and which can be used for the speed control of a pulse motor and the like by inverting the logic value of an output signal when a frequency division counter value is matched with a setting value.
SOLUTION: A reference clock signal Fc is frequency-divided by respective FF1-7 in a frequency divider 1 and respective outputs C0-6 are inputted to circuits AND1-7 in a selection part 20. The inputs are AND-operated with the respective outputs of a selector 2, all the outputs of AND1-7 are OR-operated in an OR circuit 5 and a basic clock signal Fb is obtained. The signal Fb is inputted to the counter 13 of a counter part 3 and an up-count operation is executed. When the value of the counter 13 is matched with the setting value of a setting part 50, a comparison circuit 14 resets the counter 13 and FF 15 inverts the logic value of an output signal Fout. Continuous pulse signals are outputted by permitting the counter 13 to repeat resetting and up-counting.
Inventors:
Yoichi Tanaka
Application Number:
JP26603495A
Publication Date:
June 29, 2005
Filing Date:
October 13, 1995
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS,LTD.
International Classes:
H03K23/00; H03K23/64; (IPC1-7): H03K23/64; H03K23/00
Domestic Patent References:
| JP49032905B1 | ||||
| JP57148934U |
Foreign References:
| US3746891 |
Attorney, Agent or Firm:
Keisei Nishikawa
Atsuo Mori
Atsuo Mori