PURPOSE: To obtain optionally an optional clock by feeding back a signal obtained from an output of each FF to a D input terminal of the 1st stage FF of two D FF arrays where the output and the NOT output of an oscillator is connected to a T input terminal in common.

CONSTITUTION: An output of the oscillator 1 is fed to the T input of the D FF22, 24 and also its NOT output is fed to the T input of the D FF23, 25. A Q output of the FF22 is connected to a D input of the FF24 and a Q output of the FF23 is connected to the D input of the FF25. The Q output of the FF22∼25 is connected to the D input of the FF22, 23 via NAND gates 26∼29 and an AND gate 33. Moreover, the Q output of the FF22, 23 goes to a frequency division output via NAND gates 30, 31, 32. An optional clock is obtianed in response to the signal applied to one terminal of NAND gates 26∼31 in the circuit constituted in such a way.