PURPOSE: To obtain a circuit system having the capacity of speed-up of a programmable counter having a frequency division ratio of the 0.5 unit by constituting a simple fixed frequency division circuit having a frequency division ratio of 8.5.

CONSTITUTION: When an output of a 1/2 frequency division circuit 5 goes to an H level, a 1/2 frequency division circuit 3 goes to an L level after two periods of the input clock pulse , and a 3-input NAND circuit 18 is activated. Thus, an output 11 of a 1/2 frequency division circuit 2 becomes a phase control signal of a 2-input NAND circuit 12 of a 1/2 frequency division circuit 1 via the circuit 18. If the circuit 3 is driven by the output 11 of the circuit 2, the phase of the signal from the circuit 1 is shifted for one period's share of the input clock pulse . When the signal of the circuit 3 is in the relation of phase to be driven by an output 12 of the circuit 1 conversely, no phase shift is produced. As a result, even if the signals of the circuits 1 and 2 are in any phase relation, after the phase control signal is generated, the relation goes to a prescribed phase relation. This is similar when the circuit 17 is active. Thus, 1/8.5 frequency division is attained in this way.