To frequency-divide an input pulse train changing a period, and to suppress the jitter of the frequency-divided pulse train as much as possible.

A frequency division device 1 takes a positive integer having mutually different first variable and second variable, and can frequency-divide input pulses at a division ratio representing a ratio of a second variable ratio to the first variable. The division device 1 includes a counter circuit (12) counting a reference clock having a constant frequency for a period of input pulses, and arithmetic output circuits (13 and 14) conducting arithmetic operations dividing a first count value obtained by the counter circuit into values indicated by the first variable while starting the count of the reference clock and outputting one pulse every time a second count value by the count reaches any divided value of the first count value. The division device 1 further includes a frequency dividing circuit (15) outputting pulses obtained by obtained by frequency-dividing an output pulse train of an arithmetic output circuit by a value indicated by the second variable.