PURPOSE: To prevent malfunction when 0 is given as a frequency division repetitive number data by detecting it that repeating frequency division number is zero at an OR gate, stopping an output of a counter deciding a frequency division ratio switching timing so as to fix the selection state of a data selector selecting a frequency division ratio.

CONSTITUTION: The circuit is provided with OR gates 10, 11 inputting repeating frequency division number data M, N respectively and outputting the OR of the data, and it is detected that the repeating frequency division number data M, N are zero and a low level is outputted. AND gates 7, 8 inputting the output of the OR gates 10, 11 are provided and an output of a programmable counter 5 is fed to each of the other input of the AND gates 7, 8. The output of the AND gate 7, 8 are fed to a J, K input of a JKFF 6 and the Q output of the FF6 are the input of a data selector 9. Thus, when one of the repeating frequency division number data M, N is zero, an output of the OR gate 10 or 11 goes to a low level, the AND gate 7 or 8 turned off, the output of the counter 5 is not inputted and the Q output is unchanged.