Title:
FREQUENCY DOUBLING CIRCUIT
Document Type and Number:
Japanese Patent JP3191212
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To output a signal having the duty ratio of 50% without damaging simplicity and the stability of an operation which the structure of a DLL has, by outputting output signals which a voltage control delay unit obtained by cascade-connecting first and second differential delay cells sequentially output through the use of the first and second SR flip flops and an OR gate.
SOLUTION: A phase detector 30 detects a phase difference between the input signal of a frequency f1 and a signal which is fed back from a voltage control delay unit 32 and outputs a control signal CS through a loop filter 31. The differential delay cells DDC1 and DDC2 of the voltage control delay unit 32 control operation voltage by the control signal and sequentially output signals A', A", B' and B" obtained by dividing one period of the input signal into four. Then, a doubled signal 2f1 having the duty ratio of 50% is generated through the first and second SR flip flops 33 and 34 and the OR gate 35. Thus, a circuit whose structure is simple and stable can be provided.
Inventors:
Veom Sp Kim
Joan Screen
Joan Screen
Application Number:
JP3917698A
Publication Date:
July 23, 2001
Filing Date:
February 20, 1998
Export Citation:
Assignee:
ELGE SEMICON Company Limited
International Classes:
H03B19/00; H03K5/00; H03K5/156; H03K5/13; H03L7/06; (IPC1-7): H03K5/00; H03L7/06
Domestic Patent References:
| JP9270680A |
Attorney, Agent or Firm:
Fumio Sasashima (1 person outside)