Title:
FREQUENCY MULTIPLEX SIGNAL SIMULTANEOUS BRANCHING CIRCUIT
Document Type and Number:
Japanese Patent JP2734316
Kind Code:
B2
Abstract:
PURPOSE: To reduce power consumption of the circuit by increasing a simultaneous processing channel number of the simultaneous branch circuit when digital signal processing is used to implement group demodulation.
CONSTITUTION: The simultaneous branching circuit having a reception circuit 1, an A/D converter circuit 4 in which plural A/D converters 41,42,..., 4N are connected in parallel whose input voltage range differs, a signal synthesis circuit 5 processing outputs from the A/D converters, and a digital signal processing circuit 6 separating signals for each channel is provided with a level discrimination circuit 2 discriminating a voltage level of the signal received from a base band signal and generating a level notice signal and an A/D converter selection circuit 3 outputting the base band signal only to one A/D converter in the A/D converter circuits 4 based on the level notice signal.
Inventors:
KUMAGAI TAKEO
Application Number:
JP27671592A
Publication Date:
March 30, 1998
Filing Date:
September 22, 1992
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H04J1/00; H03M1/18; (IPC1-7): H04J1/00; H03M1/18
Domestic Patent References:
| JP5767324A | ||||
| JP6271334A | ||||
| JP63142920A | ||||
| JP1241223A |
Attorney, Agent or Firm:
Suzuki Akio