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Title:
FREQUENCY MULTIPLEXING SEPARATION CIRCUIT WITH DIGITAL FILTER
Document Type and Number:
Japanese Patent JPH0746211
Kind Code:
A
Abstract:
PURPOSE: To provide demultiplexing circuit which can be applied to the variation of traffic derived from changes of both the number of channels and the band width and utilizes a polyphase network. CONSTITUTION: Frequency multiplexed carrier groups are separated by filters 1021 and 1022 , and their burst frequencies are reduced in reducers 1021 ' and 1022 ' dependently upon the band width. Polyphase networks 105a to 105d attached to a stage 104 of a delay line process individual frequency multiplexed carrier groups of the same band width by programming of one Fourier transform composite multiplexing circuit 1055 . Demultiplexing circuits 102, 103, 104, and 105 can be programmed to cope with the variance of traffic, and switching stages 1031 and 1032 are used, and the reduction filter output is connected to the input of the stage of the delay line.

Inventors:
SHIYAO YAN GUO
JIERAARU MARARU
Application Number:
JP35496492A
Publication Date:
February 14, 1995
Filing Date:
December 18, 1992
Export Citation:
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Assignee:
CENTRE NAT ETD TELECOMM
International Classes:
H04B7/015; H04J1/00; H04J1/05; H04J3/00; H04J4/00; H04L27/26; (IPC1-7): H04J3/00; H04B7/015; H04J1/00
Attorney, Agent or Firm:
Keiichi Yamamoto



 
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