To provide a frequency multiplier and multiplication method with which a duty cycle of a clock can be adjusted.
The frequency multiplier is equipped with a delay circuit for receiving a first clock to output a delay clock resulting from delaying the first clock for a predetermined time, an exclusive OR means for receiving the first clock and the delay clock to output a second clock resulting from exclusively ORing the first clock and the delay clock, and a control circuit for detecting a phase difference between the first clock and the delay clock and outputting a predetermined control signal corresponding to the detected phase difference to the delay circuit, and the control signal controls a delay quantity in the delay circuit. The delay quantity in the delay circuit is adjusted in response to the control signal, so that the frequency multiplier can automatically adjust the duty cycle of the clock to be multiplied.
BOKU SEIBAI