To provide a frequency multiplier low in power consumption and capable of selecting and outputting multiplied frequencies with a small scale circuit configuration.
Original signals a, c and phase shift signals b, d phase-shifted by ±π/2 are generated from an input frequency signal f and an output multiplication signal nf, mixing circuits 16 (17) mixes these signals and a summing amplifier 18 sums the mixed signals to output an output frequency signal fOUT. In this case, a phase inverting circuit (differential amplifier circuit 14 and a selection circuit (SEL1) 33) applies phase noninverting/inverting control to any signal to selectively output one of mixed frequency(n±1) f as the output frequency signal fOUT. Furthermore, a selection circuit (SEL2) 4 opens a switch circuit 32 to interrupt the input frequency signal (f) and to operate the mixing circuits 16, 17 as a differential amplifier circuit 25 so as to output and output multiplied signal nf as the output frequency signal fOUT.
ARIMURA KAZUYOSHI
HATTORI YOSHINOBU
FUJITSU VLSI LTD