PURPOSE: To shorten the lockup time at the start of a PLL operation by providing an intermittent operation detection circuit and an intermittent output control circuit and connecting a charge circuit to the output of the intermittent output control circuit.

CONSTITUTION: An intermittent operation control circuit 3 releases a frequency divider circuit from a set state when an intermittent operation control signal (c) goes from a high level to a low level and implements counting operation according to a clock synchronizing signal (a). After the signal (c) transits to a low state and after two clock synchronizing signals (a), the output (e) of the circuit 3 transits from a high level to a low level. An intermittent output control circuit 4 receives the output (e) of the circuit 3 to control the output to a charge pump circuit 2 to be in a high impedance state when the output (e) is at a high level. Thus, the output (f) of the circuit 2 is a normal output signal after two clock synchronizing signals (a) corresponding to a normal frequency phase comparison signal.