PURPOSE: To make the circuit constitution and to implement the efficient test without a danger of malfunction by adding a 2-input OR gate to a set/reset input of two R/S FFs so as to apply a low logic level to one input at all times.

CONSTITUTION: A 2-input OR gate structure is adopted for reset and set input terminals of R/S FFs 14, 24 and a low logic level is applied to one of the input terminals. Input terminals INIT, R, V are set to a high logic level at the initializing in the electric test and the input terminal INIT is kept to a low logic level in other cases to act the R/S FFs 14, 24 like a frequency phase comparator. In the actual operation, one input of the 2-input OR gate at the input terminal of the FFs 11, 21 receives a low logic level at both the set and reset inputs and since the R/S FFs 11, 21 are entirely symmetric, the operating time difference of the FFs 11, 21 is negligibly small. Thus, a danger of malfunction due to the operating time difference of the FFs 11, 21 is avoided.