To provide a frequency signal generator employing a PLL circuit that can optionally set a frequency of an output frequency signal.

An arithmetic circuit 12 that gives a frequency division ratio G to a frequency divider 6 of a PLL circuit, consists of an upper limit memory 17 that stores the denominator produced in the case that a fraction J of a multiplier value [N+J] is indicated by a rational number (K/L) as an upper limit value, a 1st adder 14 that sums the numerator and a feedback value, a 1st delay circuit 15 that delays the outputted sum H to give the delayed sum to the 1st adder, a 2nd delay circuit 16 that delays the sum H of the 1st adder, a comparator circuit 18 that compares the sum delayed by the 2nd delay circuit with the upper limit L of the upper limit value memory to provide an output of an output value E that is 0 when the sum is less than the upper limit value 1st or that is 1 when the sum reaches the upper limit so as to clear the 1st delay circuit, and a 2nd adder 19 that sums an integral value N of the multiplier value [N+J] and the output E of the comparator circuit to apply the sum [N+E] to the frequency divider 6 as the frequency division ratio G.