Title:
FREQUENCY SYNTHESIZER DEVICE
Document Type and Number:
Japanese Patent JPH07202691
Kind Code:
A
Abstract:
PURPOSE: To obtain a device having a fine change step for acquiring output frequency by supplying a frequency signal synthesized with a reference clock signal based on accumulation information. CONSTITUTION: An accumulation decoder 25 supplies to a variable frequency divider circuit 40 accumulation information related to a number accumulated by an accumulator circuit 15 for successively counting the digital codes in the form of numbers at the timing of accumulation clock signals. The circuit 40 selects the position of a two-position switch 54 based on the accumulation information and connects to an output 5 a signal processed by one of fixed frequency dividers 51, 52 for dividing the frequency of a reference oscillator 45 by N1 and N2 . It is preferable to form an accumulation clock signal from a synthesized frequency signal, and the operation of a frequency synthesizing device 1 can be completely synchronized with the frequency of the synthesized frequency signal.
Inventors:
PATORITSUKU ARUBEERU
ARAN BUERUNIE
BERUTORAN SARU
ARAN BUERUNIE
BERUTORAN SARU
Application Number:
JP30800994A
Publication Date:
August 04, 1995
Filing Date:
December 12, 1994
Export Citation:
Assignee:
PHILIPS ELECTRONICS NV
International Classes:
G06F1/025; H03L7/197; H03K23/66; (IPC1-7): H03L7/197
Attorney, Agent or Firm:
Tadahiko Ito (1 outside)
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