To eliminate a range, wherein a PLL circuit does not have its phase locked as to a frequency synthesizer device which varies a resolution ratio with time.

Data setting the output signal of the frequency synthesizer device are set by a frequency division ratio control circuit 7 to an N counter 9 and an A counter 10. When this timing Fck overlaps with the variation timing of the set data because of the delay time τ of the frequency division ratio control circuit 7, the N counter 9 and A counter 10 input abnormal data, so that the phase of the PLL circuit is not locked. For shifting the timing in such a case, a means 12 which inverts the clock signal of the frequency division ratio control circuit 7 and a means 13 which selects whether the clock signal is inverted or not are provided. The data output timing of the frequency ratio control circuit 7 is shifted at a region close where τ=1/Fck. Since a variable frequency divider 2 can input the frequency division ratio setting data in a correctly determined state, malfunctions will not occur. Thus, a range wherein the phase is not locked in the output signal frequency range of the frequency synthesizer can be eliminated, without increasing the current consumption for reducing the circuit delay.