PURPOSE: To shorten the frequency switching time while keeping the conventional external noise resistance characteristic of a frequency synthesizer.

CONSTITUTION: Two phase locked loops consist of 1st and 2nd phase comparator circuits 10 and 1st and 2nd filter circuits 11 which are separately provided from each other. The time constant of the 2nd filter circuit 11 of the 2nd phase locked loop is set smaller than that of the 1st filter circuit 11 of the 1st phase locked loop. Then the 1st phase locked loop having the larger time constant of the circuit 11 is actuated in a steady state where no switching of frequency is carried out. Meanwhile the 2nd phase locked loop having the smaller time constant of the circuit 11 is actuated in a frequency switching state. Thus, the excellent external noise resistance characteristic of the 1st phase locked loop is secured together with a high frequency switching speed of the 2nd phase locked loop respectively.