PURPOSE: To exclude a control operation to attain demodulation with stable L and H values and at the same time to simplify the constitution of an FSK demodulation circuit, by securing the synchronism of the pulse to be applied to the data input terminal of an FF with a differential pulse obtained for every half cycle of the input data.

CONSTITUTION: A circuit 2 converts an analog modulated signal into a digital signal after detecting the zero cross point of the analog modulated signal. A circuit 4 differentiates the digital signal for every half cycle and delivers a pulse for each differentiation. The circuits 7 and 8 are reset for each output of pulse and have a desired period to discriminate frequency signals f1 and f2 corresponding to the H and L values of the reception data signal. Both clock and data signal are supplied to an FF5. Then the pulse output sent from the circuit 8 and applied to the data input terminal of the FF5 is synchronized with the pulse output given from the circuit 4 and pplied to the clock terminal. The data signals of L and H values corresponding to the signals f1 and f2 sent from the FF5 are delivered.