PURPOSE: To obtain an FSK signal demodulator without troublesome adjustment and instability, by using a digital system.

CONSTITUTION: A reception FSK signal is inputted to a gate 21 of a DPLL circuit 6 via a reception filter and a limiter (not shown) and to a differentiation circuit 29 detecting a signal conversion point. A selection circuit 24 outputs a frequency f1 or g1 to an M-notation counter 25 in response to "1" or "0" of the output of the gate circuit 21 and the counter 25 counts this frequency signal. The counted value is compared at magnitude comparators 31 and 32, and when the said counted value is smaller than the lower limit setting value, an output 34 of the comparator 32 resets a JK-FF36 at the detection of the FSK signal changing point of the circuit 29 and sets a demodulation data signal 11 to "0". If larger, the JK-FF is set with the output of the comparator 31 and the demodulation data signal 11 is set to "1".