Title:
FUNCTION VERIFICATION SYSTEM AND METHOD AND RECORDING MEDIUM
Document Type and Number:
Japanese Patent JP3199052
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To execute function verification based on pattern matching without being conscious of the interruption of a target to be verified at its function.
SOLUTION: An interruption expected value collation part 10 collates an output result obtained when a hardware interruption is generated in a simulation model 1 with a previously stored interruption expected value pattern 9. An interruption control part 8 writes a data change due to writing in an inner register or an external storage device by interruption processing in a change value file 11. The output result of the model 1 is collated with an expected value pattern 6 previously stored in an expected value collation part 7. The collation part 7 refers to the file 11 and corrects an expected value in accordance with the data change due to writing in the inner register or the external storage device in the interruption processing.
Inventors:
Hiroki Machimura
Application Number:
JP3691199A
Publication Date:
August 13, 2001
Filing Date:
February 16, 1999
Export Citation:
Assignee:
NEC
International Classes:
G01R31/319; G06F11/25; G06F11/26; G01R31/28; G06F17/50; (IPC1-7): G06F17/50; G06F11/25
Domestic Patent References:
| JP1165877A | ||||
| JP6282599A |
Other References:
【文献】中本幸一、外7名、”リアルタイム性能解析システムProBA/RTH”、NEC技報、平成6年、Vol.47、No.6、p.42~49
Attorney, Agent or Firm:
Furuzo Satoshi (1 person outside)