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Title:
GAAS PSEUDO CMOS TRANSFER GATE
Document Type and Number:
Japanese Patent JPS6057722
Kind Code:
A
Abstract:

PURPOSE: To reduce noise by a gate drive pulse by turning on/off simultaneously an FET poled oppositely and a switching FET.

CONSTITUTION: An N-channel enhancement MESFETTN and a P-channel enhancement MESFETTP are used and a complementary drive clock pulse is fed to a gate of both FETs so as to constitute a transfer gate. In conducting the FET by applying the drive pulse to the gate, a capacitive element at an output terminal is charged by a signal charge and the drive pulse is induced as a noise charge through a capacitance between the gate and output terminal at the same time. The induced electric charge of both FETs is cancelled by the relations of WNWP and LN.WN/μNLP.WP/μP, where WN and WP are gate widths of the FETTN and TP, LN and LP are gate lengths and μN and μP are carrier mobilities respectively.


Inventors:
OONO TOMIZOU
Application Number:
JP16501183A
Publication Date:
April 03, 1985
Filing Date:
September 09, 1983
Export Citation:
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Assignee:
HITACHI MICROCUMPUTER ENG
HITACHI LTD
International Classes:
H03H19/00; H03K17/687; (IPC1-7): H03H19/00
Attorney, Agent or Firm:
Akio Takahashi