To provide a game machine which does not misidentify a transition of a switch signal.
Interruption processing includes: preservation processing (ST51) for preserving level information indicating the ON/OFF state of an input signal in a time-sequential manner; and update processing (ST53) for updating timing information INT. Main processing includes: synchronous processing (SP53) for waiting until the timing information INT is updated to a specified value; detection processing (SP55) for detecting a level change of a first signal on the basis of time transition of the first signal with reference to a data storage area; and shift processing for shifting to the synchronous processing after the detection processing is ended. The total sum of the processing time (α) from the end of the synchronous processing to the end of the shift processing and the total processing time (β) for the interruption processing are set to be not longer than the interruption period (τ) and the synchronous processing is executed preceding the detection process.
EISO ARIAKI
YOSHIMORI KOTA
JP2011104402A | 2011-06-02 | |||
JP2007130213A | 2007-05-31 | |||
JP2007037976A | 2007-02-15 | |||
JP2007151565A | 2007-06-21 | |||
JP2009297581A | 2009-12-24 | |||
JP2011104402A | 2011-06-02 | |||
JP2007130213A | 2007-05-31 | |||
JP2007037976A | 2007-02-15 | |||
JP2010172589A | 2010-08-12 |
Isabe Tsuyoshi