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Title:
GAME MACHINE
Document Type and Number:
Japanese Patent JP2014087407
Kind Code:
A
Abstract:

To provide a game machine capable of executing appropriate control operation without wasting a memory space and a circuit space.

A main control part comprises an electron device incorporating, along with a CPU, a circuit REV coping with abnormalities for resetting the CPU when not receiving clear data until monitoring time. Standby means SS3 preventing the circuit REV coping with abnormalities from functioning until standby time passes, and start means ST3 allowing the circuit REV coping with abnormalities to function based on operation of a control program when the standby operation is completed are provided. The control program includes avoidance processing for outputting clear data at each predetermined time, and the monitoring time is set longer than lapse time from when the start means functions to when the avoidance processing is firstly executed.


Inventors:
YATSUGI YUZURU
Application Number:
JP2012238060A
Publication Date:
May 15, 2014
Filing Date:
October 29, 2012
Export Citation:
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Assignee:
FUJISHOJI CO LTD
International Classes:
A63F7/02
Domestic Patent References:
JP2011104072A2011-06-02
JP2009142304A2009-07-02
JP2011254984A2011-12-22
JP2000237435A2000-09-05
JP2012166050A2012-09-06
JP2011104072A2011-06-02
JP2009142304A2009-07-02
JP2011254984A2011-12-22
JP2000237435A2000-09-05
JP2012166050A2012-09-06
Attorney, Agent or Firm:
Seiichi Nonaka
Isabe Tsuyoshi



 
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