To provide a game machine capable of achieving an RAM clear function and an error release function by a single operation switch 860a without increasing a development cost of a control program.
An operation signal from an operation switch 860a is branched into an RWMCLR signal and an error release signal, and input in a putout control MPU 4120a respectively. Consequently, the operation signal from the operation switch 860a is branched to be input in the putout control MPU 4120a as the RAM clear signal similar to an operation signal from an RAM clear switch that achieves the conventional RAM clear function. The operation signal from the operation switch 860a is branched to be input in the putout control MPU 4120a as the error release signal similar to the operation signal from an error release switch that achieves a conventional error release function.
AKIYAMA MASARU
YAMANO TOMOHITO
EGUCHI KENICHI
JPH119803A | 1999-01-19 | |||
JP2005110957A | 2005-04-28 | |||
JP2011147524A | 2011-08-04 | |||
JP2009077793A | 2009-04-16 |
Hiroto Furuta
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