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Title:
GAME MACHINE
Document Type and Number:
Japanese Patent JP2016112058
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To prevent, in advance, execution of unintended interruption processing.SOLUTION: A microcomputer includes a ROM. A vector table is assigned to memory space addresses A780h to A7A7h of the ROM. In the vector table, the memory space addresses A780h to A79Fh are used for a CALLV instruction, and the memory space addresses A7A0h to A7A7h are used for interruption processing. When a value set to the vector table is a value other than 0000h, 8000h to HPRGEND, activation of the microcomputer is limited.SELECTED DRAWING: Figure 23

Inventors:
OGURA TOSHIO
Application Number:
JP2014251143A
Publication Date:
June 23, 2016
Filing Date:
December 11, 2014
Export Citation:
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Assignee:
SANKYO CO
International Classes:
A63F5/04
Domestic Patent References:
JP2004242717A2004-09-02
JP2001190749A2001-07-17
JPS6280733A1987-04-14
Attorney, Agent or Firm:
Rock wall Fuyuki
Makoto Shiokawa
Shuji Mano



 
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